The present disclosure relates generally to processes and equipment useful for fabricating semiconductor devices, particularly with regard to forming single crystal regions on a substrate and structures that incorporate single crystal regions.
Certain semiconductor fabrication processes and associated process equipment are known for growing thin epitaxial films on the surface of a semiconductor substrate. Such processes may be utilized, for example, in the preparation of silicon-on-insulator (SOI) substrates or for providing improved control of the doping profiles in adjacent semiconductor regions. One such method, as illustrated in FIGS. 1A and 1B, utilizes a solid phase epitaxy (SPE) process to produce single crystal silicon from an amorphous silicon layer or pattern that is in contact with a single crystal seed region. Such processes may be used to form, for example, channel regions in complex three dimensional stacked devices such as SRAMs and thereby obtain device structures that have improved performance.
As illustrated in FIG. 1A, during a conventional SPE process, a single-crystal substrate 201 may have an insulating layer 202 deposited, patterned and etched to form openings 203 that expose a portion of the substrate surface. A selective epitaxial growth process may be used to fill the opening with a single-crystal silicon plug 206 with a top surface that can act as a seed region 204 over which an amorphous silicon layer or pattern 205 can be formed. As illustrated in FIG. 1B, during the subsequent SPE process the amorphous silicon layer 205 will be heated to a temperature sufficient to allow the disordered atoms of the amorphous silicon adjacent the seed region 204 to be reordered into single crystal silicon 206a. The transition between the amorphous and single-crystal configurations of the silicon atoms defines an interface 207a that appears to propagate through the amorphous layer to positions 207b more removed from the seed region 204 as the SPE process continues and more of the amorphous silicon 205 is converted to single-crystal silicon. Depending on the spacing of the original single crystal silicon regions and the duration of the SPE process, some or substantially all of the amorphous silicon can be converted to a single crystal orientation.
A conventional SPE process is illustrated in FIG. 2. As illustrated in FIG. 2, a single crystal silicon substrate 101 is typically held at room temperature (typically about 20 to 25° C.) for some period of time before being introduced into the reaction chamber for epitaxial processing, a native silicon dioxide layer 104 will typically be present on the surface of the silicon substrate. This silicon dioxide layer 104, will typically be removed using a wet etch process incorporating a solution of hydrofluoric acid, HF, to prepare the substrate for additional processing.
As illustrated in FIG. 2, after the single crystal silicon substrate 101 is placed in the reactor, it may initially be exposed to a potentially oxidizing ambient, e.g., air, but as the substrate temperature is increased, the ambient within the reactor will typically be modified to suppress oxidation. These modifications may include reducing the pressure within the reactor chamber and/or introducing a non-oxidizing ambient, such as nitrogen (N2) or argon (Ar) to suppress the growth of oxide on the exposed silicon surface region(s) of the substrate. This shift to a non-oxidizing ambient will typically be initiated at a temperature below about 350° C.
However, despite the shift to a non-oxidizing ambient as the substrate temperature is ramping up into the process temperature range, residual oxygen and/or water within the reactor chamber and/or absorbed on the substrate may result in the formation of a silicon oxide layer (SiOx) 102 on the order of 10 to 15 Å on the surface of the substrate, particularly as the temperature is ramped above 350° C. In a conventional SPE process, the temperature of the substrate and the adjacent reactor chamber components will generally be ramped to and then stabilized or maintained for some period at or near a target deposition temperature, typically about 620° C.
Once the reaction chamber and single crystal silicon substrate 101 have been stabilized at the target deposition temperature, a silicon-containing gas such as silane (SiH4) may be introduced into the reaction chamber with nitrogen (N2) to deposit a silicon thin film 103 on the substrate. However, the presence of the silicon oxide film 102 on the silicon substrate will tend to interfere with the orderly epitaxial formation of a single-crystal silicon film which results in the formation of a substantially polycrystalline silicon thin film 103. Further, with the silicon oxide film 102 interposed between the silicon substrate 101 and the silicon thin film 103, the contact resistance between the two silicon regions will tend to be increased.